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ORCIDInternational Journal of High Performance Systems Architecture, Volume 2
Volume 2, Number 1, 2009
- D. Meganathan
, J. Raja Paul Perinbam, R. Deepalakshmi:
High speed, low power 100 MS/s front end track-and-hold amplifier for ten-bit pipelined ADC. 1-15 - Fabiane Cristine Dillenburg, Jorge Luis Victória Barbosa:
Context-oriented exception handling. 16-25 - Alexandre Solon Nery, Nadia Nedjah, Felipe M. G. França:
A massively parallel hardware architecture for ray-tracing. 26-34 - Subhendu Kumar Sahoo, Chandra Shekhar, Sudeepti Kodali, Abhijit R. Asati, Anu Gupta:
Dual channel addition based FFT processor architecture for signal and image processing. 35-45 - Marcus Vinícius Carvalho da Silva, Nadia Nedjah, Luiza de Macedo Mourelle:
Efficient mapping of an image processing application for a network-on-chip based implementation. 46-57 - Thatyana de Faria Piola Seraphim, Enzo Seraphim, Gonzalo Travieso:
HieraAnalyses - a tool for hierarchical analysis of parallel programs. 58-67
Volume 2, Number 2, 2009
- Ricardo Santos, Rafael Batistella, Rodolfo Azevedo:
A pattern based instruction encoding technique for high performance architectures. 71-80 - João V. F. Lima, Nicolas Maillard:
Online mapping of MPI-2 dynamic tasks to processes and threads. 81-89 - Leandro Sales, Henrique Teofilo, Nabor C. Mendonça, Jonathan D'Orleans, Rafael G. Barbosa, Fernando A. M. Trinta:
An evaluation of the performance impact of generic group communication APIs. 90-98 - Douglas Dyllon Jeronimo de Macedo, Aldo von Wangenheim, Mario A. R. Dantas, Hilton Ganzo William Perantunes:
An architecture for DICOM medical images storage and retrieval adopting distributed file systems. 99-106 - Cristiano Bonato Both, Cristiano Battisti, Felipe A. Kuentzer, Tatiana Gadelha Serra dos Santos, Rafael R. dos Santos:
FPGA implementation and performance evaluation of an RFC 2544 compliant Ethernet test set. 107-115 - Bernardo Fortunato Costa, Marta Mattoso, Inês de Castro Dutra:
Applying reinforcement learning to scheduling strategies in an actual grid environment. 116-128
Volume 2, Numbers 3/4, 2010
- Pavel Ghosh, Arunabha Sen:
Energy efficient mapping and voltage islanding for regular NoC under design constraints. 132-144 - Xiongli Gu, Peng Liu, Zhiyuan Xu, Bingjie Xia, Cheng Li, Qingdong Yao, Ce Shi:
A synergetic operating unit on NoC layer for CMP system. 145-155 - Yoon Seok Yang, Jun Ho Bahn, Seung Eun Lee, Jungsook Yang, Nader Bagherzadeh:
Parallel processing for block ciphers on a fault tolerant networked processor array. 156-167 - Bingjie Xia, Kejun Wu, Chunchang Xiang, Mei Yang, Peng Liu, Qingdong Yao:
Network interface design based on mutual interface definition. 168-176 - George Kornaros:
NCXplore: a design space exploration framework of temporal encoding for on-chip serial interconnects. 177-186 - Danilo Pani, Francesca Palumbo, Luigi Raffo:
A fast MPI-based parallel framework for cycle-accurate HDL multi-parametric simulations. 187-202 - Christipher D. Jenkins, Michael J. Schulte, John Glossner:
Instruction set extensions for the advanced encryption standard on a multithreaded software defined radio platform. 203-214 - Alessandro Bardine, Manuel Comparetti, Pierfrancesco Foglia, Giacomo Gabrielli, Cosimo Antonio Prete:
Way adaptable D-NUCA caches. 215-228 - Wei Zhang:
Replica victim caching to improve cache reliability against transient errors. 229-239 - Fangyang Shen, Andrés O. Salazar, Xiao Qin, Min-Te Sun:
A reliability model of energy-efficient parallel disk systems with data mirroring. 240-249
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