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ORCID25th VDAT 2021: Surat, India
- 25th International Symposium on VLSI Design and Test, VDAT 2021, Surat, India, September 16-18, 2021. IEEE 2021, ISBN 978-1-6654-1992-5
- Alish Kanani
, Swar Vaidya, Harshit Agarwal:
LightFPGA: Scalable and Automated FPGA Acceleration of LightGBM for Machine Learning Applications. 1-6 - K. Lakshmi BhanuPrakash Reddy, K. B. Dheeraj Kumar, Vikramkumar Pudi:
Design of Energy-Efficient TSPC based D Flip-flop for CNTFET Technology. 1-4 - T. R. Varun, Rajasekhar Nagulapalli, Immanuel Raja:
A 82μW Mixed-Mode sub-1V Bandgap reference with 25 ppm/°C Temperature Co-efficient with Simultaneous PTAT Generation. 1-4 - Raman Thukral, Mohit Goswami, Sharayu Jagtap, Sandeep Goyal, Shalabh Gupta:
A Multi-Octave Frequency Range SerDes with a DLL Free Receiver. 1-6 - Deepak K. Sharma, J. John, G. Supriya, Ashwini Jambhalikar, M. S. Giridhar:
Process Development for Very Deep Etching of Silicon Using Two Layer Masks for Fabrication of Mechanically Decoupled MEMS Gyroscope. 1-4 - Takshashila Pathade, Yash Agrawal, Rutu Parekh, Girish Kumar Mekala:
CNTFET Based Low Power Repeaters for On-Chip Interconnect System. 1-4 - Sahibia Kaur Vohra, Sherin A. Thomas, Mahendra Sakare, Devarshi Mrinal Das:
Analytical Modelling of a CMOS Inter Spike Interval Decoder for Resistive Crossbar based Brain Inspired Computing. 1-4 - Yuvam Bhateja, Joshua Roy Palathinkal, Tamajeet Mandal, Pronay Roy, Dipankar Saha:
Modeling of Thermal Properties of Semiconducting Monolayer MoSe2 and WSe2. 1-6 - Jay Pathak, Anand D. Darji:
Analysis of Standard Cells performance for In0.53Ga0.47As FinFET with underlap fin length for High Speed Applications. 1-4 - Nirmal Kumar Boran, Kenrick Pinto, Bernard Menezes:
On Disabling Prefetcher to Amplify Cache Side Channels. 1-6 - Ayazulla Khan Patan, Dimitrios Stathis, Pudi Dhilleswararao, Yu Yang, Srinivas Boppu, Ahmed Hemani:
Design and Implementation of Optimized Register File for Streaming Applications. 1-4 - Mahesh Mahadurkar, Nalesh Sivanandan, S. Kala:
Hardware Acceleration of SpMV Multiplier for Deep Learning. 1-6 - Abi K. Krishnan, M. H. Supriya, Nalesh Sivanandan:
A Hardware-Software Co-design based Approach for Development of a Distributed DAQ System using FPGA. 1-6 - Venkata Reddy Kolagatla, Vivian Desalphine, David Selvakumar:
Area-Time Scalable High Radix Montgomery Modular Multiplier for Large Modulus. 1-4 - S. Sharon Dev, S. M. Krishna, S. S. Archana, Rose George Kunthara, K. Neethu, Rekha K. James:
Dual Stage Encoding Technique to Minimize Cross Coupling across NoC Links. 1-6 - P. Saravanan, J. Jenitha, S. R. Aasish, S. Sanjana:
Quantum Circuit Design of RECTANGLE Lightweight Cipher. 1-4 - Kaushal Kumari Neeraj, Nihar Ranjan Mohapatra:
Behavior of LDMOS transistors at cryogenic temperature - An experiment based analysis. 1-4 - Diksha Shekhawat, Apoorva Jangir, Jai Gopal Pandey:
A Hardware Generator for Posit Arithmetic and its FPGA Prototyping. 1-6 - Rahul Mukherjee, Joydeep Basu, Prasanta Kumar Guha:
High Sensitivity and Power Efficient Heater Structure for Bulk Micromachined Thermal Accelerometer. 1-4 - Ganesh Mulay, Himanshu N. Patel, Manish Kumar, Kiral Ghodadra:
FPGA based High Frequency Clock Phase Difference Measurement and Correction. 1-4 - Sarita Yadav, Nitanshu Chauhan, Archana Pandey, Rajendra Pratap, Anand Bulusu:
Behaviour of FinFET Inverter's Effective Capacitances in Low-Voltage Domain. 1-5 - Shubham, Chetan Pathak, Saurabh Kumar Pandey:
Comprehensive Study and Photovoltaic Performance Analysis of Eco-friendly Perovskite Solar Cell. 1-5 - Mythrai, Pragna, Kavitha S, Pooran Singh, A. P. Shah, S. K. Vishwakarma, Bhupendra Singh Reniwal:
Energy Efficient, Hamming Code Technique for Error Detection/Correction Using In-Memory Computation. 1-4 - Tresa Joseph, T. S. Bindiya:
High Speed and Power Efficient Multiplexer based Matrix Vector Multiplication for LSTM Network. 1-4 - Saurabh Katre, Shubham Tirmanwar, Debapratim Ghosh:
Broadband CMOS RF Logarithmic Power Detector for sub-6 GHz 5G Applications. 1-4 - Soumya Tapse, Srivatsava Jandhyala, Adithya Reddy Banti:
An All-CMOS Supply, Temperature and Process Invariant Hybrid Current Reference For Power Efficient IoT Applications. 1-4 - Soma Barman Mandal, Moumita Acharya, Samik Basu, Amlan Chakrabarti:
FPGA Implementation of Different Stochastic Biochemical Reactions Involved in a Cell. 1-4 - David Selvakumar, J. Mervin, Shashikala Gunderao Pattanshetty, Vivian Desalphine:
Formal Verification and Analysis of a Pseudo Random Number Generator. 1-6 - Ashish Sura, Vikas Nehra:
Performance Comparison of Single Level STT and SOT MRAM Cells for Cache Applications. 1-4 - Sayeed Ahmad, Naushad Alam, Mohd. Hasan:
Radiation Hardened Area-Efficient 10T SRAM Cell for Space Applications. 1-6 - S. Devi, Gourav Tilwankar, Rajesh Zele:
Automated Design of Analog Circuits using Machine Learning Techniques. 1-6 - Venkata Reddy Kolagatla, J. Mervin, Shabbir Darbar, David Selvakumar, Sankha Saha:
A Randomized Montgomery Powering Ladder Exponentiation for Side-Channel Attack Resilient RSA and Leakage Assessment. 1-5 - Yatin Kumar Gupta, Yash Agrawal, Rutu Parekh, Bakul Gohel:
Assessment of Emerging Graphene based Network-on-chip for Integrated Circuit Design. 1-4
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