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ORCIDMEDEA@PACT 2008: Toronto, Canada
- Pierfrancesco Foglia, Cosimo Antonio Prete, Sandro Bartolini, Roberto Giorgi:
Proceedings of the 9th workshop on MEmory performance - DEaling with Applications, systems and architecture, MEDEA '08, Toronto, Canada, October 26, 2008. ACM 2008, ISBN 978-1-60558-243-6 - Jaydeep Marathe, Frank Mueller:
PFetch: software prefetching exploiting temporal predictability of memory access streams. 1-8 - Isao Kotera, Ryusuke Egawa, Hiroyuki Takizawa
, Hiroaki Kobayashi:
Modeling of cache access behavior based on Zipf's law. 9-15 - Mafijul Md. Islam, Per Stenström:
Zero loads: canceling load requests by tracking zero values. 16-23 - Akihiro Musa, Yoshiei Sato, Takashi Soga, Koki Okabe, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi:
A shared cache for a chip multi vector processor. 24-29 - Hyunhee Kim, Sungjun Youn, Jihong Kim:
A leakage-aware cache sharing technique for low-power chip multi-processors (CMPs) with private L2 caches. 30-37 - Stefan Metzlaff, Sascha Uhrig, Jörg Mische, Theo Ungerer:
Predictable dynamic instruction scratchpad for simultaneous multithreaded processors. 38-45 - Layali K. Rashid, Wessam M. Hassanein, Moustafa A. Hammad:
Exploiting multithreaded architectures to improve the hash join operation. 46-53 - Mitchell Hayenga, Chander Sudanthi, Mrinmoy Ghosh, Prakash Ramrakhyani, Nigel C. Paver:
Accurate system-level performance modeling and workload characterization for mobile internet devices. 54-60 - Ferad Zyulkyarov, Adrián Cristal, Sanja Cvijic, Eduard Ayguadé, Mateo Valero, Osman S. Unsal, Tim Harris:
WormBench: a configurable workload for evaluating transactional memory systems. 61-68 - Marc Lupon, Grigorios Magklis, Antonio González:
Version management alternatives for hardware transactional memory. 69-76 - Roger Ferrer, Marc González, Federico Silla, Xavier Martorell, Eduard Ayguadé:
Evaluation of memory performance on the cell BE with the SARC programming model. 77-84
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