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ORCIDHOST 2019: McLean, VA, USA
- IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2019, McLean, VA, USA, May 5-10, 2019. IEEE 2019, ISBN 978-1-5386-8064-3
- Brice Colombier, Alexandre Menu, Jean-Max Dutertre, Pierre-Alain Moëllic, Jean-Baptiste Rigaud
, Jean-Luc Danger:
Laser-induced Single-bit Faults in Flash Memory: Instructions Corruption on a 32-bit Microcontroller. 1-10 - Debayan Das, Mayukh Nath, Baibhab Chatterjee, Santosh Ghosh, Shreyas Sen:
STELLAR: A Generic EM Side-Channel Attack Protection through Ground-Up Root-cause Analysis. 11-20 - Chiou-Yng Lee, Jiafeng Xie:
High Capability and Low-Complexity: Novel Fault Detection Scheme for Finite Field Multipliers over GF(2m) based on MSPB. 21-30 - Nikhil Chawla, Arvind Singh, Nael Mizanur Rahman, Monodeep Kar, Saibal Mukhopadhyay:
Extracting Side-Channel Leakage from Round Unrolled Implementations of Lightweight Ciphers. 31-40 - Keyvan Ramezanpour, Paul Ampadu, William Diehl:
A Statistical Fault Analysis Methodology for the Ascon Authenticated Cipher. 41-50 - Karthikeyan Nagarajan, Mohammad Nasim Imtiaz Khan, Swaroop Ghosh:
ENTT: A Family of Emerging NVM-based Trojan Triggers. 51-60 - Qihang Shi, Nidish Vashistha, Hangwei Lu, Hao-Ting Shen, Bahar Tehranipoor, Damon L. Woodard, Navid Asadizanjani:
Golden Gates: A New Hybrid Approach for Rapid Hardware Trojan Detection using Testing and Imaging. 61-71 - Ujjwal Guin, Wendong Wang, Charles Harper, Adit D. Singh:
Detecting Recycled SoCs by Exploiting Aging Induced Biases in Memory Cells. 72-80 - Adam Duncan, Grant Skipper, Andrew Stern, Adib Nahiyan, Fahim Rahman, Andrew Lukefahr, Mark M. Tehranipoor, Martin Swany:
FLATS: Filling Logic and Testing Spatially for FPGA Authentication and Tamper Detection. 81-90 - Xiaolong Guo, Raj Gautam Dutta, Jiaji He, Mark M. Tehranipoor, Yier Jin:
QIF-Verilog: Quantitative Information-Flow based Hardware Description Languages for Pre-Silicon Security Assessment. 91-100 - Patrick Cronin, Chengmo Yang:
A Fetching Tale: Covert Communication with the Hardware Prefetcher. 101-110 - Shijia Wei, Aydin Aysu, Michael Orshansky, Andreas Gerstlauer, Mohit Tiwari:
Using Power-Anomalies to Counter Evasive Micro-Architectural Attacks in Embedded Systems. 111-120 - Fan Yao, Hongyu Fang, Milos Doroslovacki, Guru Venkataramani:
COTSknight: Practical Defense against Cache Timing Channel Attacks using Cache Monitoring and Partitioning Technologies. 121-130 - Mohammed Nabeel, Mohammed Ashraf, Eduardo Chielle, Nektarios Georgios Tsoutsos, Michail Maniatakos:
CoPHEE: Co-processor for Partially Homomorphic Encrypted Execution. 131-140 - Tim Fritzmann, Johanna Sepúlveda:
Efficient and Flexible Low-Power NTT for Lattice-Based Cryptography. 141-150 - Michaela Brunner, Johanna Baehr, Georg Sigl:
Improving on State Register Identification in Sequential Hardware Reverse Engineering. 151-160 - Kaveh Shamsi, David Z. Pan, Yier Jin:
On the Impossibility of Approximation-Resilient Circuit Locking. 161-170 - Suyuan Chen, Ranga Vemuri:
Exploiting Proximity Information in a Satisfiability Based Attack Against Split Manufactured Circuits. 171-180 - Prabuddha Chakraborty, Jonathan Cruz, Swarup Bhunia:
SURF: Joint Structural Functional Attack on Logic Locking. 181-190 - Ge Li, Vishnuvardhan V. Iyer, Michael Orshansky:
Securing AES against Localized EM Attacks through Spatial Randomization of Dataflow. 191-197 - M. Sadegh Riazi, Mojan Javaheripi, Siam U. Hussain, Farinaz Koushanfar:
MPCircuits: Optimized Circuit Generation for Secure Multi-Party Computation. 198-207 - Daniel Dinu, Archanaa S. Krishnan, Patrick Schaumont:
SIA: Secure Intermittent Architecture for Off-the-Shelf Resource-Constrained Microcontrollers. 208-217 - Manaar Alam, Sarani Bhattacharya, Swastika Dutta, Sayan Sinha, Debdeep Mukhopadhyay, Anupam Chattopadhyay:
RATAFIA: Ransomware Analysis using Time And Frequency Informed Autoencoders. 218-227 - Michael Tempelmeier, Maximilian Werner, Georg Sigl:
Using Hardware Software Codesign for Optimised Implementations of High-Speed and Defence in Depth CAESAR Finalists. 228-237 - Andreas Herkle, Holger Mandry, Joachim Becker, Maurits Ortmanns:
In-depth Analysis and Enhancements of RO-PUFs with a Partial Reconfiguration Framework on Xilinx Zynq-7000 SoC FPGAs. 238-247
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