BibTeX record journals/vlsisp/NevesF97

download as .bib file

@article{DBLP:journals/vlsisp/NevesF97,
  author       = {Jos{\'{e}} Luis Neves and
                  Eby G. Friedman},
  title        = {Buffered Clock Tree Synthesis with Non-Zero Clock Skew Scheduling
                  for Increased Tolerance to Process Parameter Variations},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {16},
  number       = {2-3},
  pages        = {149--161},
  year         = {1997},
  url          = {https://doi.org/10.1023/A:1007986907060},
  doi          = {10.1023/A:1007986907060},
  timestamp    = {Wed, 20 May 2020 21:26:21 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/NevesF97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
a service of  Schloss Dagstuhl - Leibniz Center for Informatics

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.