BibTeX record journals/tvlsi/ChatterjeeS05

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@article{DBLP:journals/tvlsi/ChatterjeeS05,
  author       = {Bhaskar Chatterjee and
                  Manoj Sachdev},
  title        = {Design of a 1.7-GHz low-power delay-fault-testable 32-b {ALU} in 180-nm
                  {CMOS} technology},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {13},
  number       = {11},
  pages        = {1296--1304},
  year         = {2005},
  url          = {https://doi.org/10.1109/TVLSI.2005.859563},
  doi          = {10.1109/TVLSI.2005.859563},
  timestamp    = {Wed, 11 Mar 2020 18:18:38 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/ChatterjeeS05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

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