BibTeX record journals/tjs/GaoWXYLQZC18

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@article{DBLP:journals/tjs/GaoWXYLQZC18,
  author       = {Lan Gao and
                  Rui Wang and
                  Yunlong Xu and
                  Hailong Yang and
                  Zhongzhi Luan and
                  Depei Qian and
                  Han Zhang and
                  Jihong Cai},
  title        = {{SRAM-} and STT-RAM-based hybrid, shared last-level cache for on-chip
                  {CPU-GPU} heterogeneous architectures},
  journal      = {J. Supercomput.},
  volume       = {74},
  number       = {7},
  pages        = {3388--3414},
  year         = {2018},
  url          = {https://doi.org/10.1007/s11227-018-2389-3},
  doi          = {10.1007/S11227-018-2389-3},
  timestamp    = {Fri, 22 May 2020 13:26:46 +0200},
  biburl       = {https://dblp.org/rec/journals/tjs/GaoWXYLQZC18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

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