Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"SRAM- and STT-RAM-based hybrid, shared last-level cache for on-chip ..."

Lan Gao et al. (2018)

> Home

Details and statistics

DOI: 10.1007/S11227-018-2389-3

access: closed

type: Journal Article

metadata version: 2020-05-22

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/tjs/GaoWXYLQZC18
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tjs/GaoWXYLQZC18
Lan Gao, Rui Wang, Yunlong Xu, Hailong Yang, Zhongzhi Luan, Depei Qian, Han Zhang, Jihong Cai:
SRAM- and STT-RAM-based hybrid, shared last-level cache for on-chip CPU-GPU heterogeneous architectures. J. Supercomput. 74(7): 3388-3414 (2018)

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.