@article{DBLP:journals/tc/VasudevanVSA07,
  author    = {Shobha Vasudevan and
               Vinod Viswanath and
               Robert W. Sumners and
               Jacob A. Abraham},
  title     = {Automatic Verification of Arithmetic Circuits in RTL Using
               Stepwise Refinement of Term Rewriting Systems},
  journal   = {IEEE Trans. Computers},
  volume    = {56},
  number    = {10},
  year      = {2007},
  pages     = {1401-1414},
  ee        = {http://doi.ieeecomputersociety.org/10.1109/TC.2007.1073},
  bibsource = {DBLP, http://dblp.uni-trier.de}
}