BibTeX record journals/scjapan/YonedaSN97

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@article{DBLP:journals/scjapan/YonedaSN97,
  author       = {Tomohiro Yoneda and
                  Atsufumi Shibayama and
                  Takashi Nanya},
  title        = {Verification of asynchronous logic circuit design using process algebra},
  journal      = {Syst. Comput. Jpn.},
  volume       = {28},
  number       = {8-9},
  pages        = {33--43},
  year         = {1997},
  url          = {https://doi.org/10.1002/(SICI)1520-684X(199708)28:8\<33::AID-SCJ5\>3.0.CO;2-M},
  doi          = {10.1002/(SICI)1520-684X(199708)28:8\<33::AID-SCJ5\>3.0.CO;2-M},
  timestamp    = {Wed, 13 Sep 2023 17:54:10 +0200},
  biburl       = {https://dblp.org/rec/journals/scjapan/YonedaSN97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

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