Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"Verification of asynchronous logic circuit design using process algebra."

Tomohiro Yoneda, Atsufumi Shibayama, Takashi Nanya (1997)

> Home

Details and statistics

DOI: 10.1002/(SICI)1520-684X(199708)28:8<33::AID-SCJ5>3.0.CO;2-M

access: closed

type: Journal Article

metadata version: 2023-09-13

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/scjapan/YonedaSN97
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/scjapan/YonedaSN97
Tomohiro Yoneda, Atsufumi Shibayama, Takashi Nanya:
Verification of asynchronous logic circuit design using process algebra. Syst. Comput. Jpn. 28(8-9): 33-43 (1997)

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.