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BibTeX record journals/jssc/WelB12
@article{DBLP:journals/jssc/WelB12, author = {Arnoud P. van der Wel and Gerrit den Besten}, title = {A 1.2-6 Gb/s, 4.2 pJ/Bit Clock {\&} Data Recovery Circuit With High Jitter Tolerance in 0.14 {\(\mathrm{\mu}\)}m {CMOS}}, journal = {{IEEE} J. Solid State Circuits}, volume = {47}, number = {7}, pages = {1768--1775}, year = {2012}, url = {https://doi.org/10.1109/JSSC.2012.2191318}, doi = {10.1109/JSSC.2012.2191318}, timestamp = {Sun, 30 Aug 2020 00:13:36 +0200}, biburl = {https://dblp.org/rec/journals/jssc/WelB12.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
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