BibTeX record journals/jssc/HuangRBCKH03

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@article{DBLP:journals/jssc/HuangRBCKH03,
  author       = {Xuejue Huang and
                  Phillip J. Restle and
                  Thomas J. Bucelot and
                  Yu Cao and
                  Tsu{-}Jae King and
                  Chenming Hu},
  title        = {Loop-based interconnect modeling and optimization approach for multigigahertz
                  clock network design},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {38},
  number       = {3},
  pages        = {457--463},
  year         = {2003},
  url          = {https://doi.org/10.1109/JSSC.2002.808313},
  doi          = {10.1109/JSSC.2002.808313},
  timestamp    = {Fri, 07 Oct 2022 16:41:25 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/HuangRBCKH03.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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