BibTeX record journals/jpdc/PalchaudhuriD21

download as .bib file

@article{DBLP:journals/jpdc/PalchaudhuriD21,
  author       = {Ayan Palchaudhuri and
                  Anindya Sundar Dhar},
  title        = {Speed-area optimized {VLSI} architecture of multi-bit cellular automaton
                  cell based random number generator on {FPGA} with testable logic support},
  journal      = {J. Parallel Distributed Comput.},
  volume       = {151},
  pages        = {13--23},
  year         = {2021},
  url          = {https://doi.org/10.1016/j.jpdc.2021.01.005},
  doi          = {10.1016/J.JPDC.2021.01.005},
  timestamp    = {Thu, 29 Apr 2021 15:15:03 +0200},
  biburl       = {https://dblp.org/rec/journals/jpdc/PalchaudhuriD21.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
a service of  Schloss Dagstuhl - Leibniz Center for Informatics

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.