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"Speed-area optimized VLSI architecture of multi-bit cellular automaton ..."

Ayan Palchaudhuri, Anindya Sundar Dhar (2021)

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DOI: 10.1016/J.JPDC.2021.01.005

access: closed

type: Journal Article

metadata version: 2021-04-29

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Ayan Palchaudhuri, Anindya Sundar Dhar:
Speed-area optimized VLSI architecture of multi-bit cellular automaton cell based random number generator on FPGA with testable logic support. J. Parallel Distributed Comput. 151: 13-23 (2021)

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