BibTeX record journals/integration/WangTTLWC16

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@article{DBLP:journals/integration/WangTTLWC16,
  author       = {Po{-}Hao Wang and
                  Shang{-}Jen Tsai and
                  Rizal Tanjung and
                  Tay{-}Jyi Lin and
                  Jinn{-}Shyan Wang and
                  Tien{-}Fu Chen},
  title        = {Cross-matching caches: Dynamic timing calibration and bit-level timing-failure
                  mask caches to reduce timing discrepancies with low voltage processors},
  journal      = {Integr.},
  volume       = {54},
  pages        = {24--36},
  year         = {2016},
  url          = {https://doi.org/10.1016/j.vlsi.2016.01.001},
  doi          = {10.1016/J.VLSI.2016.01.001},
  timestamp    = {Thu, 20 Feb 2020 13:21:27 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/WangTTLWC16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}