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"Cross-matching caches: Dynamic timing calibration and bit-level ..."

Po-Hao Wang et al. (2016)

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DOI: 10.1016/J.VLSI.2016.01.001

access: closed

type: Journal Article

metadata version: 2020-02-20

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Po-Hao Wang, Shang-Jen Tsai, Rizal Tanjung, Tay-Jyi Lin, Jinn-Shyan Wang, Tien-Fu Chen:
Cross-matching caches: Dynamic timing calibration and bit-level timing-failure mask caches to reduce timing discrepancies with low voltage processors. Integr. 54: 24-36 (2016)

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