BibTeX record conf/vlsit/ZhangZCQLWL23

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@inproceedings{DBLP:conf/vlsit/ZhangZCQLWL23,
  author       = {Zhao Zhang and
                  Zhaoyu Zhang and
                  Yong Chen and
                  Nan Qi and
                  Jian Liu and
                  Nanjian Wu and
                  Liyuan Liu},
  title        = {A 64-Gb/s Reference-Less {PAM4} {CDR} with Asymmetrical Linear Phase
                  Detector Soring 231.5-fsrms Clock Jitter and 0.21-pJ/bit Energy Efficiency
                  in 40-nm {CMOS}},
  booktitle    = {2023 {IEEE} Symposium on {VLSI} Technology and Circuits {(VLSI} Technology
                  and Circuits), Kyoto, Japan, June 11-16, 2023},
  pages        = {1--2},
  publisher    = {{IEEE}},
  year         = {2023},
  url          = {https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185285},
  doi          = {10.23919/VLSITECHNOLOGYANDCIR57934.2023.10185285},
  timestamp    = {Sat, 27 Jul 2024 13:40:02 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsit/ZhangZCQLWL23.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}