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ORCID"A 64-Gb/s Reference-Less PAM4 CDR with Asymmetrical Linear Phase Detector ..."
Zhao Zhang et al. (2023)
- Zhao Zhang, Zhaoyu Zhang, Yong Chen, Nan Qi, Jian Liu, Nanjian Wu, Liyuan Liu:
A 64-Gb/s Reference-Less PAM4 CDR with Asymmetrical Linear Phase Detector Soring 231.5-fsrms Clock Jitter and 0.21-pJ/bit Energy Efficiency in 40-nm CMOS. VLSI Technology and Circuits 2023: 1-2
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last updated on 2023-11-02 12:25 CET by the dblp team
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