BibTeX record conf/vlsit/KimYCCLLLYDTLSB23

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@inproceedings{DBLP:conf/vlsit/KimYCCLLLYDTLSB23,
  author       = {Jeongkyun Kim and
                  Byungho Yook and
                  Taemin Choi and
                  Kyuwon Choi and
                  Chanho Lee and
                  Yunrong Li and
                  Youngo Lee and
                  Seok Yun and
                  Changhoon Do and
                  Hoyoung Tang and
                  Inhak Lee and
                  Dongwook Seo and
                  Sangyeop Baeck},
  title        = {A 4.0GHz {UHS} Pseudo Two-port {SRAM} with {BL} Charge Time Reduction
                  and Flying Word-Line for {HPC} Applications in 4nm FinFET Technology},
  booktitle    = {2023 {IEEE} Symposium on {VLSI} Technology and Circuits {(VLSI} Technology
                  and Circuits), Kyoto, Japan, June 11-16, 2023},
  pages        = {1--2},
  publisher    = {{IEEE}},
  year         = {2023},
  url          = {https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185223},
  doi          = {10.23919/VLSITECHNOLOGYANDCIR57934.2023.10185223},
  timestamp    = {Tue, 07 May 2024 20:11:30 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsit/KimYCCLLLYDTLSB23.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}