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"A 4.0GHz UHS Pseudo Two-port SRAM with BL Charge Time Reduction and Flying ..."

Jeongkyun Kim et al. (2023)

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DOI: 10.23919/VLSITECHNOLOGYANDCIR57934.2023.10185223

access: closed

type: Conference or Workshop Paper

metadata version: 2024-05-07

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  - https://dblp.org/rec/conf/vlsit/KimYCCLLLYDTLSB23
Jeongkyun Kim, Byungho Yook, Taemin Choi, Kyuwon Choi, Chanho Lee, Yunrong Li, Youngo Lee, Seok Yun, Changhoon Do, Hoyoung Tang, Inhak Lee, Dongwook Seo, Sangyeop Baeck:
A 4.0GHz UHS Pseudo Two-port SRAM with BL Charge Time Reduction and Flying Word-Line for HPC Applications in 4nm FinFET Technology. VLSI Technology and Circuits 2023: 1-2

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