BibTeX record conf/vlsid/GhoshNP94

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@inproceedings{DBLP:conf/vlsid/GhoshNP94,
  author       = {Debabrata Ghosh and
                  S. K. Nandy and
                  K. Parthasarathy},
  title        = {{TWTXBB:} {A} Low Latency, High Throughput Multiplier Architecture
                  Using a New 4 --{\textgreater} 2 Compressor},
  booktitle    = {Proceedings of the Seventh International Conference on {VLSI} Design,
                  {VLSI} Design 1994, Calcutta, India, January 5-8, 1994},
  pages        = {77--82},
  publisher    = {{IEEE} Computer Society},
  year         = {1994},
  url          = {https://doi.org/10.1109/ICVD.1994.282660},
  doi          = {10.1109/ICVD.1994.282660},
  timestamp    = {Fri, 24 Mar 2023 00:03:59 +0100},
  biburl       = {https://dblp.org/rec/conf/vlsid/GhoshNP94.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}