BibTeX record conf/vlsic/ZhangLGWYQWPSO20

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@inproceedings{DBLP:conf/vlsic/ZhangLGWYQWPSO20,
  author       = {Yuncheng Zhang and
                  Bangan Liu and
                  Xiaofan Gu and
                  Chun Wang and
                  Kiyoshi Yanagisawa and
                  Junjun Qiu and
                  Yun Wang and
                  Jian Pang and
                  Atsushi Shirane and
                  Kenichi Okada},
  title        = {A 29{\%} {PAE} 1.5Bit-DSM-Based Polar Transmitter with Spur-Mitigated
                  Injection-Locked {PLL}},
  booktitle    = {{IEEE} Symposium on {VLSI} Circuits, {VLSI} Circuits 2020, Honolulu,
                  HI, USA, June 16-19, 2020},
  pages        = {1--2},
  publisher    = {{IEEE}},
  year         = {2020},
  url          = {https://doi.org/10.1109/VLSICircuits18222.2020.9162955},
  doi          = {10.1109/VLSICIRCUITS18222.2020.9162955},
  timestamp    = {Fri, 09 Apr 2021 18:36:40 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsic/ZhangLGWYQWPSO20.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}