BibTeX record conf/vlsic/HudnerCCHNCEPLZ18

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@inproceedings{DBLP:conf/vlsic/HudnerCCHNCEPLZ18,
  author       = {James Hudner and
                  Declan Carey and
                  Ronan Casey and
                  Kay Hearne and
                  Pedro Wilson de Abreu Farias Neto and
                  Ilias Chlis and
                  Marc Erett and
                  Chi Fung Poon and
                  Asma Laraba and
                  Hongtao Zhang and
                  Sai Lalith Chaitanya Ambatipudi and
                  David Mahashin and
                  Parag Upadhyaya and
                  Yohan Frans and
                  Ken Chang},
  title        = {A 112GB/S {PAM4} Wireline Receiver Using a 64-Way Time-Interleaved
                  {SAR} {ADC} in 16NM FinFET},
  booktitle    = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
                  18-22, 2018},
  pages        = {47--48},
  publisher    = {{IEEE}},
  year         = {2018},
  url          = {https://doi.org/10.1109/VLSIC.2018.8502436},
  doi          = {10.1109/VLSIC.2018.8502436},
  timestamp    = {Thu, 30 Sep 2021 15:01:32 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsic/HudnerCCHNCEPLZ18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}