BibTeX record conf/vlsi-dat/WuCLLW17

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@inproceedings{DBLP:conf/vlsi-dat/WuCLLW17,
  author       = {Chia{-}Heng Wu and
                  Ting{-}Sheng Chen and
                  Ding{-}Yuan Lee and
                  Tsung{-}Te Liu and
                  An{-}Yeu Wu},
  title        = {Low-latency Voltage-Racing Winner-Take-All {(VR-WTA)} circuit for
                  acceleration of learning engine},
  booktitle    = {2017 International Symposium on {VLSI} Design, Automation and Test,
                  {VLSI-DAT} 2017, Hsinchu, Taiwan, April 24-27, 2017},
  pages        = {1--4},
  publisher    = {{IEEE}},
  year         = {2017},
  url          = {https://doi.org/10.1109/VLSI-DAT.2017.7939641},
  doi          = {10.1109/VLSI-DAT.2017.7939641},
  timestamp    = {Wed, 16 Oct 2019 14:14:54 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsi-dat/WuCLLW17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}