BibTeX record conf/sips/LinSWZC07

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@inproceedings{DBLP:conf/sips/LinSWZC07,
  author       = {Su{-}Hon Lin and
                  Ming{-}Hwa Sheu and
                  Kuang{-}Hui Wang and
                  Jun{-}Jie Zhu and
                  Si{-}Ying Chen},
  title        = {Efficient {VLSI} Design of Modulo 2\({}^{\mbox{n}}\)-1 Adder Using
                  Hybrid Carry Selection},
  booktitle    = {Proceedings of the {IEEE} Workshop on Signal Processing Systems, SiPS
                  2007, Proceedings, October 17-19, 2007, Eton Hotel, Shanghai, China},
  pages        = {142--145},
  publisher    = {{IEEE}},
  year         = {2007},
  url          = {https://doi.org/10.1109/SIPS.2007.4387534},
  doi          = {10.1109/SIPS.2007.4387534},
  timestamp    = {Sun, 21 May 2017 00:20:17 +0200},
  biburl       = {https://dblp.org/rec/conf/sips/LinSWZC07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}