BibTeX record conf/patmos/VerleMMAA03

• > Home > conf/patmos/VerleMMAA03

@inproceedings{DBLP:conf/patmos/VerleMMAA03,
  author       = {Alexandre Verle and
                  Xavier Michel and
                  Philippe Maurine and
                  Nadine Az{\'{e}}mard and
                  Daniel Auvergne},
  editor       = {Jorge Juan{-}Chico and
                  Enrico Macii},
  title        = {{CMOS} Gate Sizing under Delay Constraint},
  booktitle    = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
                  and Simulation, 13th International Workshop, {PATMOS} 2003, Torino,
                  Italy, September 10-12, 2003, Proceedings},
  series       = {Lecture Notes in Computer Science},
  volume       = {2799},
  pages        = {60--69},
  publisher    = {Springer},
  year         = {2003},
  url          = {https://doi.org/10.1007/978-3-540-39762-5\_8},
  doi          = {10.1007/978-3-540-39762-5\_8},
  timestamp    = {Tue, 14 May 2019 10:00:54 +0200},
  biburl       = {https://dblp.org/rec/conf/patmos/VerleMMAA03.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}