BibTeX record conf/memsys/HameedMC17

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@inproceedings{DBLP:conf/memsys/HameedMC17,
  author       = {Fazal Hameed and
                  Christian Menard and
                  Jer{\'{o}}nimo Castrill{\'{o}}n},
  title        = {Efficient {STT-RAM} last-level-cache architecture to replace {DRAM}
                  cache},
  booktitle    = {Proceedings of the International Symposium on Memory Systems, {MEMSYS}
                  2017, Alexandria, VA, USA, October 02 - 05, 2017},
  pages        = {141--151},
  publisher    = {{ACM}},
  year         = {2017},
  url          = {https://doi.org/10.1145/3132402.3132414},
  doi          = {10.1145/3132402.3132414},
  timestamp    = {Mon, 05 Feb 2024 20:35:24 +0100},
  biburl       = {https://dblp.org/rec/conf/memsys/HameedMC17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

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