BibTeX record conf/isqed/YanoHS13

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@inproceedings{DBLP:conf/isqed/YanoHS13,
  author       = {Ken Yano and
                  Takanori Hayashida and
                  Toshinori Sato},
  title        = {Improving timing error tolerance without impact on chip area and power
                  consumption},
  booktitle    = {International Symposium on Quality Electronic Design, {ISQED} 2013,
                  Santa Clara, CA, USA, March 4-6, 2013},
  pages        = {373--378},
  publisher    = {{IEEE}},
  year         = {2013},
  url          = {https://doi.org/10.1109/ISQED.2013.6523638},
  doi          = {10.1109/ISQED.2013.6523638},
  timestamp    = {Fri, 27 Dec 2019 21:24:29 +0100},
  biburl       = {https://dblp.org/rec/conf/isqed/YanoHS13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

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