BibTeX record conf/isicir/AoHLWL14

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@inproceedings{DBLP:conf/isicir/AoHLWL14,
  author       = {Kun Ao and
                  Yajuan He and
                  Liang Li and
                  Yuxin Wang and
                  Qiang Li},
  title        = {A 14-bit 100MS/s pipelined {A/D} converter with 2b interstage redundancy},
  booktitle    = {2014 International Symposium on Integrated Circuits (ISIC), Singapore,
                  December 10-12, 2014},
  pages        = {83--86},
  publisher    = {{IEEE}},
  year         = {2014},
  url          = {https://doi.org/10.1109/ISICIR.2014.7029486},
  doi          = {10.1109/ISICIR.2014.7029486},
  timestamp    = {Wed, 09 Dec 2020 14:38:50 +0100},
  biburl       = {https://dblp.org/rec/conf/isicir/AoHLWL14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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