BibTeX record conf/ic3/JaiswalS17

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@inproceedings{DBLP:conf/ic3/JaiswalS17,
  author       = {Ramanand Jaiswal and
                  Trailokya Nath Sasamal},
  editor       = {Srinivas Alum and
                  Ananth Kalyanaraman and
                  Bora U{\c{c}}ar and
                  Kishore Kothapalli and
                  Mahantesh Halappanavar and
                  Kamesh Madduri and
                  Madhu Govindaraju and
                  Yinglong Xia and
                  Sushil K. Prasad and
                  Martina Barnas and
                  Ashish Sureka and
                  Pankesh Patel and
                  Vikas Saxena and
                  Sanjay Goel},
  title        = {Efficient design of full adder and subtractor using 5-input majority
                  gate in {QCA}},
  booktitle    = {Tenth International Conference on Contemporary Computing, {IC3} 2017,
                  Noida, India, August 10-12, 2017},
  pages        = {1--6},
  publisher    = {{IEEE} Computer Society},
  year         = {2017},
  url          = {https://doi.org/10.1109/IC3.2017.8284336},
  doi          = {10.1109/IC3.2017.8284336},
  timestamp    = {Fri, 24 Mar 2023 00:03:21 +0100},
  biburl       = {https://dblp.org/rec/conf/ic3/JaiswalS17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}