Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"Efficient design of full adder and subtractor using 5-input majority gate ..."

Ramanand Jaiswal, Trailokya Nath Sasamal (2017)

> Home

Details and statistics

DOI: 10.1109/IC3.2017.8284336

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

- view
  authority control:
- export record
  dblp key:
  - conf/ic3/JaiswalS17
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/ic3/JaiswalS17
Ramanand Jaiswal, Trailokya Nath Sasamal:
Efficient design of full adder and subtractor using 5-input majority gate in QCA. IC3 2017: 1-6

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.