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@inproceedings{DBLP:conf/ftcs/SiehTB97,
author = {Volkmar Sieh and
Oliver Tsch{\"a}che and
Frank Balbach},
title = {VERIFY: Evaluation of Reliability Using VHDL-Models with
Embedded Fault Descriptions},
booktitle = {FTCS},
year = {1997},
pages = {32-36},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Copyright © 2002-01-03 by Michael Ley (ley@uni-trier.de)