"VERIFY: Evaluation of Reliability Using VHDL-Models with Embedded Fault ..."

Volkmar Sieh, Oliver Tschäche, Frank Balbach (1997)

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DOI: 10.1109/FTCS.1997.614074

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Volkmar Sieh, Oliver Tschäche, Frank Balbach:
VERIFY: Evaluation of Reliability Using VHDL-Models with Embedded Fault Descriptions. FTCS 1997: 32-36

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