BibTeX record conf/coolchips/HagiwaraHKAENTN18

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@inproceedings{DBLP:conf/coolchips/HagiwaraHKAENTN18,
  author       = {Kesami Hagiwara and
                  Tomoichi Hayashi and
                  Shumpei Kawasaki and
                  Fumio Arakawa and
                  Oleg Endo and
                  Hayato Nomura and
                  Akira Tsukamoto and
                  Duong Nguyen and
                  Binh Nguyen and
                  Anh Tran and
                  Hoan Hyunh and
                  Ikuo Kudoh and
                  Cong{-}Kha Pham},
  title        = {A two-stage-pipeline {CPU} of {SH-2} architecture implemented on {FPGA}
                  and SoC for IoT, edge {AI} and robotic applications},
  booktitle    = {2018 {IEEE} Symposium in Low-Power and High-Speed Chips, {COOL} {CHIPS}
                  2018, Yokohama, Japan, April 18-20, 2018},
  pages        = {1--3},
  publisher    = {{IEEE} Computer Society},
  year         = {2018},
  url          = {https://doi.org/10.1109/CoolChips.2018.8373084},
  doi          = {10.1109/COOLCHIPS.2018.8373084},
  timestamp    = {Thu, 23 Mar 2023 23:58:22 +0100},
  biburl       = {https://dblp.org/rec/conf/coolchips/HagiwaraHKAENTN18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}