BibTeX record conf/aspdac/YodaTK99

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@inproceedings{DBLP:conf/aspdac/YodaTK99,
  author       = {Tomoyuki Yoda and
                  Atsushi Takahashi and
                  Yoji Kajitani},
  title        = {Clock Period Minimization of Semi-Synchronous Circuits by Gate-Level
                  Delay Insertion},
  booktitle    = {Proceedings of the 1999 Conference on Asia South Pacific Design Automation,
                  Wanchai, Hong Kong, China, January 18-21, 1999},
  pages        = {125},
  publisher    = {{IEEE} Computer Society},
  year         = {1999},
  url          = {https://doi.org/10.1109/ASPDAC.1999.759775},
  doi          = {10.1109/ASPDAC.1999.759775},
  timestamp    = {Mon, 01 May 2023 13:01:28 +0200},
  biburl       = {https://dblp.org/rec/conf/aspdac/YodaTK99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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