Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"Clock Period Minimization of Semi-Synchronous Circuits by Gate-Level Delay ..."

Tomoyuki Yoda, Atsushi Takahashi, Yoji Kajitani (1999)

> Home

Details and statistics

DOI: 10.1109/ASPDAC.1999.759775

access: closed

type: Conference or Workshop Paper

metadata version: 2023-05-01

- view
  authority control:
- export record
  dblp key:
  - conf/aspdac/YodaTK99
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/aspdac/YodaTK99
Tomoyuki Yoda, Atsushi Takahashi, Yoji Kajitani:
Clock Period Minimization of Semi-Synchronous Circuits by Gate-Level Delay Insertion. ASP-DAC 1999: 125-

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.