@inproceedings{DBLP:conf/aspdac/WuKHLL10,
  author    = {Tsung-Yi Wu and
               Tzi-Wei Kao and
               Shi-Yi Huang and
               Tai-Lun Li and
               How-Rern Lin},
  title     = {Combined use of rising and falling edge triggered clocks
               for peak current reduction in IP-based SoC designs},
  booktitle = {ASP-DAC},
  year      = {2010},
  pages     = {444-449},
  ee        = {http://dx.doi.org/10.1109/ASPDAC.2010.5419842},
  crossref  = {DBLP:conf/aspdac/2010},
  bibsource = {DBLP, http://dblp.uni-trier.de}
}

@proceedings{DBLP:conf/aspdac/2010,
  title     = {Proceedings of the 15th Asia South Pacific Design Automation
               Conference, ASP-DAC 2010, Taipei, Taiwan, January 18-21,
               2010},
  booktitle = {ASP-DAC},
  publisher = {IEEE},
  year      = {2010},
  isbn      = {978-1-60558-837-7},
  bibsource = {DBLP, http://dblp.uni-trier.de}
}