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"Combined use of rising and falling edge triggered clocks for peak current ..."

Tsung-Yi Wu et al. (2010)

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DOI: 10.1109/ASPDAC.2010.5419842

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

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  - https://dblp.org/rec/conf/aspdac/WuKHLL10
Tsung-Yi Wu, Tzi-Wei Kao, Shi-Yi Huang, Tai-Lun Li, How-Rern Lin:
Combined use of rising and falling edge triggered clocks for peak current reduction in IP-based SoC designs. ASP-DAC 2010: 444-449

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