BibTeX record conf/asicon/ZhangCYR19

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@inproceedings{DBLP:conf/asicon/ZhangCYR19,
  author       = {Shumin Zhang and
                  Yuefeng Cao and
                  Fan Ye and
                  Junyan Ren},
  title        = {A 10b 250MS/s {SAR} {ADC} with Speed-Enhanced {SAR} Logic and Free
                  Time More Than a Half of Sampling Period},
  booktitle    = {13th {IEEE} International Conference on ASIC, {ASICON} 2019, Chongqing,
                  China, October 29 - November 1, 2019},
  pages        = {1--4},
  publisher    = {{IEEE}},
  year         = {2019},
  url          = {https://doi.org/10.1109/ASICON47005.2019.8983593},
  doi          = {10.1109/ASICON47005.2019.8983593},
  timestamp    = {Tue, 29 Dec 2020 18:39:26 +0100},
  biburl       = {https://dblp.org/rec/conf/asicon/ZhangCYR19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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