BibTeX record conf/apccas/FujiwaraAKYT14

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@inproceedings{DBLP:conf/apccas/FujiwaraAKYT14,
  author       = {Koichi Fujiwara and
                  Shin{-}ya Abe and
                  Kazushi Kawamura and
                  Masao Yanagisawa and
                  Nozomu Togawa},
  title        = {A floorplan-aware high-level synthesis algorithm for multiplexer reduction
                  targeting {FPGA} designs},
  booktitle    = {2014 {IEEE} Asia Pacific Conference on Circuits and Systems, {APCCAS}
                  2014, Ishigaki, Japan, November 17-20, 2014},
  pages        = {244--247},
  publisher    = {{IEEE}},
  year         = {2014},
  url          = {https://doi.org/10.1109/APCCAS.2014.7032765},
  doi          = {10.1109/APCCAS.2014.7032765},
  timestamp    = {Sun, 25 Oct 2020 23:06:31 +0100},
  biburl       = {https://dblp.org/rec/conf/apccas/FujiwaraAKYT14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}