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"A floorplan-aware high-level synthesis algorithm for multiplexer reduction ..."

Koichi Fujiwara et al. (2014)

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DOI: 10.1109/APCCAS.2014.7032765

access: closed

type: Conference or Workshop Paper

metadata version: 2020-10-25

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Koichi Fujiwara, Shin-ya Abe, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa:
A floorplan-aware high-level synthesis algorithm for multiplexer reduction targeting FPGA designs. APCCAS 2014: 244-247

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