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ORCIDYuji Osaki
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- affiliation: Kobe University, Japan
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Journal Articles
- 2014
[j7]Keishi Tsubaki, Tetsuya Hirose, Yuji Osaki, Seiichiro Shiga, Nobutaka Kuroki, Masahiro Numa:
A Fully On-Chip, 6.66-kHz, 320-nA, 56ppm/°C, CMOS Relaxation Oscillator with PVT Variation Compensation Circuit. IEICE Trans. Electron. 97-C(6): 512-518 (2014)- 2013
- [j6]Igors Homjakovs, Tetsuya Hirose, Yuji Osaki, Masanori Hashimoto
, Takao Onoye:
A 0.8-V 110-nA CMOS current reference circuit using subthreshold operation. IEICE Electron. Express 10(4): 20130022 (2013) - [j5]Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa:
1.2-V Supply, 100-nW, 1.09-V Bandgap and 0.7-V Supply, 52.5-nW, 0.55-V Subbandgap Reference Circuits for Nanowatt CMOS LSIs. IEEE J. Solid State Circuits 48(6): 1530-1538 (2013) - 2012
- [j4]Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa:
A Low-Power Level Shifter With Logic Error Correction for Extremely Low-Voltage Digital CMOS LSIs. IEEE J. Solid State Circuits 47(7): 1776-1783 (2012) - 2011
- [j3]Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa:
A wide input voltage range level shifter circuit for extremely low-voltage digital LSIs. IEICE Electron. Express 8(12): 890-896 (2011) - [j2]Yuji Osaki, Tetsuya Hirose, Kei Matsumoto, Nobutaka Kuroki, Masahiro Numa:
Robust Subthreshold CMOS Digital Circuit Design with On-Chip Adaptive Supply Voltage Scaling Technique. IEICE Trans. Electron. 94-C(1): 80-88 (2011) - [j1]Kei Matsumoto, Tetsuya Hirose, Yuji Osaki, Nobutaka Kuroki, Masahiro Numa:
Subthreshold SRAM with Write Assist Technique Using On-Chip Threshold Voltage Monitoring Circuit. IEICE Trans. Electron. 94-C(6): 1042-1048 (2011)
Conference and Workshop Papers
- 2012
- [c6]Yumiko Tsuruya, Tetsuya Hirose, Yuji Osaki, Nobutaka Kuroki, Masahiro Numa, Osamu Kobayashi:
A nano-watt power CMOS amplifier with adaptive biasing for power-aware analog LSIs. ESSCIRC 2012: 69-72 - [c5]Keishi Tsubaki, Tetsuya Hirose, Yuji Osaki, Seiichiro Shiga, Nobutaka Kuroki, Masahiro Numa:
A 6.66-kHz, 940-nW, 56ppm/°C, fully on-chip PVT variation tolerant CMOS relaxation oscillator. ICECS 2012: 97-100 - [c4]Yuji Osaki, Tetsuya Hirose, Keishi Tsubaki, Nobutaka Kuroki, Masahiro Numa:
A low-power single-slope analog-to-digital converter with digital PVT calibration. ICECS 2012: 613-616 - 2011
- [c3]Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa:
A 95-nA, 523ppm/°C, 0.6-μW CMOS current reference circuit with subthreshold MOS resistor ladder. ASP-DAC 2011: 113-114 - [c2]Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa:
A level shifter with logic error correction circuit for extremely low-voltage digital CMOS LSIs. ESSCIRC 2011: 199-202 - 2010
- [c1]Tetsuya Hirose, Yuji Osaki, Nobutaka Kuroki, Masahiro Numa:
A nano-ampere current reference circuit and its temperature dependence control by using temperature characteristics of carrier mobilities. ESSCIRC 2010: 114-117
Coauthor Index
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