Erik Jan Marinissen

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Vikram Iyengar

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Publications

2003
[j10]
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Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen:
Test Access Mechanism Optimization, Test Scheduling, and Tester Data Volume Reduction for System-on-Chip. IEEE Trans. Computers 52(12): 1619-1632 (2003)
[j9]
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Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen:
Efficient test access mechanism optimization for system-on-chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(5): 635-643 (2003)
2002
[j6]
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Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen:
Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip. J. Electron. Test. 18(2): 213-230 (2002)
[c21]
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Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen:
Recent Advances in Test Planning for Modular Testing of Core-Based SOCs. Asian Test Symposium 2002: 320-
[c20]
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Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen:
Wrapper/TAM co-optimization, constraint-driven test scheduling, and tester data volume reduction for SOCs. DAC 2002: 685-690
[c19]
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Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen:
Efficient Wrapper/TAM Co-Optimization for Large SOCs. DATE 2002: 491-498
[c17]
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Erik Jan Marinissen, Vikram Iyengar, Krishnendu Chakrabarty:
A Set of Benchmarks fo Modular Testing of SOCs. ITC 2002: 519-528
[c15]
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Vikram Iyengar, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty:
Test Resource Optimization for Multi-Site Testing of SOCs Under ATE Memory Depth Constraints. ITC 2002: 1159-1168
[c14]
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Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen:
On Using Rectangle Packing for SOC Wrapper/TAM Co-Optimization. VTS 2002: 253-258
2001
[c11]
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  - conf/itc/IyengarCM01
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Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen:
Test wrapper and test access mechanism co-optimization for system-on-chip. ITC 2001: 1023-1032

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