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ORCIDDimitris Nikolos
- > Home > Persons > Dimitris Nikolos
Publications
- 2007
[j36]Themistoklis Haniotakis, Y. Tsiatouhas, Dimitris Nikolos, Costas Efstathiou:
Testable Designs of Multiple Precharged Domino Circuits. IEEE Trans. Very Large Scale Integr. Syst. 15(4): 461-465 (2007)- 2005
- [j31]Costas Efstathiou, Haridimos T. Vergos, Giorgos Dimitrakopoulos
, Dimitris Nikolos:
Efficient Diminished-1 Modulo 2^n+1 Multipliers. IEEE Trans. Computers 54(4): 491-496 (2005) - [c63]Giorgos Dimitrakopoulos, Dimitris G. Nikolos, Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou:
New architectures for modulo 2N - 1 adders. ICECS 2005: 1-4 - [c62]Giorgos Dimitrakopoulos, Dimitris G. Nikolos, Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou:
New architectures for modulo 2N - 1 adders. ICECS 2005: 1-4 - 2004
- [j30]Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos:
Modified Booth Modulo 2n-1 Multipliers. IEEE Trans. Computers 53(3): 370-374 (2004) - [j29]Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos:
Fast Parallel-Prefix Modulo 2^n+1 Adders. IEEE Trans. Computers 53(9): 1211-1216 (2004) - 2003
- [j27]Haridimos T. Vergos, Dimitris Nikolos, Maciej Bellos, Costas Efstathiou:
Deterministic BIST for RNS Adders. IEEE Trans. Computers 52(7): 896-906 (2003) - [j26]Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos:
Modulo 2n±1 Adder Design Using Select-Prefix Blocks. IEEE Trans. Computers 52(11): 1399-1406 (2003) - [c52]Giorgos Dimitrakopoulos, Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou:
A Family of Parallel-Pre.x Modulo 2n - 1 Adders. ASAP 2003: 326-336 - [c50]Costas Efstathiou, Haridimos T. Vergos, Giorgos Dimitrakopoulos, Dimitris Nikolos:
Efficient modulo 2n+1 tree multipliers for diminished-1 operands. ICECS 2003: 200-203 - [c49]Dimitris G. Nikolos, Dimitris Nikolos, Haridimos T. Vergos, Costas Efstathiou:
An Efficient BIST scheme for High-Speed Adders. IOLTS 2003: 89-93 - [c48]Dimitris G. Nikolos, Dimitris Nikolos, Haridimos T. Vergos, Costas Efstathiou:
An Efficient BIST scheme for High-Speed Adders. IOLTS 2003: 89-93 - [c47]Giorgos Dimitrakopoulos, Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou:
A systematic methodology for designing area-time efficient parallel-prefix modulo 2n - 1 adders. ISCAS (5) 2003: 225-228 - [c45]Dimitris G. Nikolos, Dimitris Nikolos, Haridimos T. Vergos, Costas Efstathiou:
Efficient BIST schemes for RNS datapaths. ISCAS (5) 2003: 573-576 - [c44]Dimitris G. Nikolos, Dimitris Nikolos, Haridimos T. Vergos, Costas Efstathiou:
Efficient BIST schemes for RNS datapaths. ISCAS (5) 2003: 573-576 - 2002
- [j21]Haridimos T. Vergos, Costas Efstathiou, Dimitris Nikolos:
Diminished-One Modulo 2n+1 Adder Design. IEEE Trans. Computers 51(12): 1389-1399 (2002) - [c39]Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos:
Ling adders in CMOS standard cell technologies. ICECS 2002: 485-488 - 2001
- [c34]Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou:
High Speed Parallel-Prefix Modulo 2n+1 Adders for Diminished-One Operands. IEEE Symposium on Computer Arithmetic 2001: 211-217 - [c32]Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos:
On the design of modulo 2n±1 adders. ICECS 2001: 517-520 - [c30]Y. Tsiatouhas, Th. Haniotakis, Dimitris Nikolos, Costas Efstathiou:
Concurrent Detection of Soft Errors Based on Current Monitoring. IOLTW 2001: 106-110 - [c28]Haridimos T. Vergos, Dimitris Nikolos, Maciej Bellos, Costas Efstathiou:
A Formal Test Set for RNS Adders and an Efficient Low Power BIST Scheme. LATW 2001: 242-247 - 2000
- [j18]Lampros Kalampoukas, Dimitris Nikolos, Costas Efstathiou, Haridimos T. Vergos, John Kalamatianos:
High-Speed Parallel-Prefix Modulo 2n-1 Adders. IEEE Trans. Computers 49(7): 673-680 (2000) - [c24]Th. Haniotakis, Y. Tsiatouhas, Dimitris Nikolos, Costas Efstathiou:
On Testability of Multiple Precharged Domino Logic. ISQED 2000: 299-304
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