Bram Nauta

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Simon M. Louwsma

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Publications

2019
[c88]
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Harijot Singh Bindra, Anne-Johan Annema, Gerard Wienk, Bram Nauta, Simon M. Louwsma:
A 4MS/s 10b SAR ADC with integrated Class-A buffers in 65nm CMOS with near rail-to-rail input using a single 1.2V supply. CICC 2019: 1-4
[c86]
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Harijot Singh Bindra, Anne-Johan Annema, Simon M. Louwsma, Bram Nauta:
A 0.2 - 8 MS/s 10b flexible SAR ADC achieving 0.35 - 2.5 fJ/conv-step and using self-quenched dynamic bias comparator. VLSI Circuits 2019: 74-
2017
[c84]
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Harijot Singh Bindra, Joeri Lechevallier, Anne-Johan Annema, Simon M. Louwsma, Ed van Tuijl, Bram Nauta:
Range pre-selection sampling technique to reduce input drive energy for SAR ADCs. A-SSCC 2017: 217-220
[c79]
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Harijot Singh Bindra, Anne-Johan Annema, Simon M. Louwsma, Ed J. M. van Tuijl, Bram Nauta:
An energy reduced sampling technique applied to a 10b 1MS/s SAR ADC. ESSCIRC 2017: 235-238
2008
[j37]
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  - journals/jssc/LouwsmaTVN08
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Simon M. Louwsma, A. J. M. van Tuijl, Maarten Vertregt, Bram Nauta:
A 1.35 GS/s, 10 b, 175 mW Time-Interleaved AD Converter in 0.13 µm CMOS. IEEE J. Solid State Circuits 43(4): 778-786 (2008)
2007
[c22]
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Simon M. Louwsma, Ed van Tuijl, Maarten Vertregt, Bram Nauta:
A Time-Interleaved Track & hold in 0.13 μm CMOS sub-sampling a 4 GHz signal with 43 dB SNDR. CICC 2007: 329-332
2004
[j11]
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Eric A. M. Klumperink, Simon M. Louwsma, Gerard J. M. Wienk, Bram Nauta:
A CMOS switched transconductor mixer. IEEE J. Solid State Circuits 39(8): 1231-1240 (2004)
[c4]
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Simon M. Louwsma, Ed J. M. van Tuijl, Maarten Vertregt, Peter C. S. Scholtens, Bram Nauta:
A 1.6 GS/s, 16 times interleaved track & hold with 7.6 ENOB in 0.12 μm CMOS [ADC applications]. ESSCIRC 2004: 343-346

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