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Kanemitsu Ootsu
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Publications
- 2019
- [j11]Takanobu Baba, Shinpei Watanabe, Boaz Jessie Jackin, Kanemitsu Ootsu, Takeshi Ohkawa, Takashi Yokota, Yoshio Hayasaki, Toyohiko Yatagai:
Fast Computation with Efficient Object Data Distribution for Large-Scale Hologram Generation on a Multi-GPU Cluster. IEICE Trans. Inf. Syst. 102-D(7): 1310-1320 (2019) - 2018
- [c45]Takanobu Baba, Shinpei Watanabe, Boaz Jessie Jackin, Kanemitsu Ootsu, Takeshi Ohkawa, Takashi Yokota, Yoshio Hayasaki, Toyohiko Yatagai:
Data Distribution Method for Fast Giga-scale Hologram Generation on a Multi-GPU Cluster. ApPLIED@PODC 2018: 37-40 - [c44]Takanobu Baba, Shinpei Watanabe, Boaz Jessie Jackin, Takeshi Ohkawa, Kanemitsu Ootsu, Takashi Yokota, Yoshio Hayasaki, Toyohiko Yatagai:
Overcoming the difficulty of large-scale CGH generation on multi-GPU cluster. GPGPU@PPoPP 2018: 13-21 - 2017
- [c40]Shinpei Watanabe, Boaz Jessie Jackin, Takeshi Ohkawa, Kanemitsu Ootsu, Takashi Yokota, Yoshio Hayasaki, Toyohiko Yatagai, Takanobu Baba:
Acceleration of Large-Scale CGH Generation Using Multi-GPU Cluster. CANDAR 2017: 589-593 - 2015
- [c29]Kanemitsu Ootsu, Yutaka Matsuno, Takeshi Ohkawa, Takashi Yokota, Takanobu Baba:
Empirical performance study of speculative parallel processing on commercial multi-core CPU with hardware transactional memory. SEPS@SPLASH 2015: 57-65 - 2013
- [j4]Yuanming Zhang, Kanemitsu Ootsu, Takashi Yokota, Takanobu Baba:
An automatic thread decomposition approach for pipelined multithreading. Int. J. High Perform. Comput. Netw. 7(3): 227-237 (2013) - [j3]Takeshi Ohkawa, Daichi Uetake, Takashi Yokota, Kanemitsu Ootsu, Takanobu Baba:
Reconfigurable and hardwired ORB engine on FPGA by Java-to-HDL synthesizer for realtime application. SIGARCH Comput. Archit. News 41(5): 77-82 (2013) - [c25]Hiroyoshi Jutori, Takanobu Baba, Kanemitsu Ootsu, Takeshi Ohkawa, Takashi Yokota:
Exploration of Highly Accurate Path Prediction Mechanism Using Detailed Path History. CANDAR 2013: 582-586 - 2012
- [c23]Kazuhiro Kinkai, Takanobu Baba, Hiroyoshi Jutori, Kanemitsu Ootsu, Takeshi Ohkawa, Takashi Yokota:
Comparative Study of Path Prediction Method for Speculative Loop Execution. ICNC 2012: 283-287 - [c22]Atsushi Shina, Kanemitsu Ootsu, Takeshi Ohkawa, Takashi Yokota, Takanobu Baba:
Proposal of Incremental Software Simulation for Reduction of Evaluation Time. ICNC 2012: 311-315 - 2011
- [c21]Takashi Yokota, Kanemitsu Ootsu, Takanobu Baba:
Steady/Unsteady Communication Performance in Large-Scale Regular Networks. AINA Workshops 2011: 727-732 - 2010
- [c20]Kanemitsu Ootsu, Takeshi Abe, Takashi Yokota, Takanobu Baba:
Loop Performance Improvement for Min-cut Program Decomposition Method. ICNC 2010: 78-87 - [c19]Yuanming Zhang, Kanemitsu Ootsu, Takashi Yokota, Takanobu Baba:
Automatic Thread Decomposition for Pipelined Multithreading. ICPADS 2010: 91-98 - 2009
- [c18]Takashi Yokota, Kanemitsu Ootsu, Takanobu Baba:
An Effective Throttling Method Based on Quasi-global Congestion Information. ISPAN 2009: 104-109 - [c17]Yuanming Zhang, Kanemitsu Ootsu, Takashi Yokota, Takanobu Baba:
Clustered Software Queue for Efficient Pipelined Multithreading. PDCAT 2009: 116-123 - 2008
- [c16]Takashi Yokota, Kanemitsu Ootsu, Takanobu Baba:
Potentials of Branch Predictors: From Entropy Viewpoints. ARCS 2008: 273-285 - [c15]Yuanming Zhang, Kanemitsu Ootsu, Takashi Yokota, Takanobu Baba:
Clustered Decoupled Software Pipelining on Commodity CMP. ICPADS 2008: 681-688 - [c14]Takashi Yokota, Kanemitsu Ootsu, Takanobu Baba:
Are Uniform Nerworks Scalable? PDCAT 2008: 137-140 - 2007
- [c13]Takashi Yokota, Kanemitsu Ootsu, Takanobu Baba:
Introducing entropies for representing program behavior and branch predictor performance. Experimental Computer Science 2007: 17 - [c11]Kanemitsu Ootsu, Takahiko Kobayashi, Takashi Yokota, Takanobu Baba:
A thread partitioning technique for multithreaded execution along hot paths. Parallel and Distributed Computing and Networks 2007: 278-282 - 2006
- [c10]Takashi Yokota, Kanemitsu Ootsu, Fumihito Furukawa, Takanobu Baba:
Entropy Throttling: A Physical Approach for Maximizing Packet Mobility in Interconnection Networks. Asia-Pacific Computer Systems Architecture Conference 2006: 309-322 - 2005
- [c9]Takashi Yokota, Masashi Nishitani, Kanemitsu Ootsu, Fumihito Furukawa, Takanobu Baba:
Cross-Line - A Globally Adaptive Control Method of Interconnection Network. ISHPC 2005: 191-198 - [c8]Takashi Yokota, Moriyuki Saito, Fumihito Furukawa, Kanemitsu Ootsu, Takanobu Baba:
Two-Path Limited Speculation Method for Static/Dynamic Optimization in Multithreaded Systems. PDCAT 2005: 46-50 - [c7]Atsushi Tsukikawa, Fumihito Furukawa, Takayuki Aoki, Daisuke Oka, Kanemitsu Ootsu, Takashi Yokota, Takanobu Baba:
Design and Implementation of a VLIW Processor Simulation Environment with Instruction Scheduling Framework. IASTED PDCS 2005: 536-541 - 2003
- [j2]Yoshiyuki Iwamoto, Koichi Suga, Kanemitsu Ootsu, Takashi Yokota, Takanobu Baba:
Receiving message prediction method. Parallel Comput. 29(11-12): 1509-1538 (2003) - 2002
- [c6]Takashi Yokota, Masamichi Nagafuchi, Yoshito Mekada, Tsutomu Yoshinaga, Kanemitsu Ootsu, Takanobu Baba:
A Scalable FPGA-Based Custom Computing Machine for a Medical Image Processing. FCCM 2002: 307-308 - [c5]Takashi Yokota, Masamichi Nagafuchi, Yoshito Mekada, Tsutomu Yoshinaga, Kanemitsu Ootsu, Takanobu Baba:
Real-Time Medical Diagnosis on a Multiple FPGA-based System. FPL 2002: 1088-1091 - [c4]Kanemitsu Ootsu, Takafumi Ono, Takashi Yokota, Takanobu Baba:
A Methodology of Binary-level Multithreading and Its Preliminary Evaluation. IASTED PDCS 2002: 792-797 - 2001
- [c3]Kanemitsu Ootsu, Tsutomu Yoshinaga, Takanobu Baba:
Design and Evaluation of Speculative Multi-threading with Selective Multi-Path Execution. IPDPS 2001: 139 - 2000
- [j1]Takanobu Baba, Tsutomu Yoshinaga, Yoshiyuki Iwamoto, Kanemitsu Ootsu:
Design, Implementation and Evaluation of a Parallel Object-Oriented Language A-NETL. Scalable Comput. Pract. Exp. 3(2) (2000) - [c2]Tsutomu Yoshinaga, Masaya Hayashi, Maki Horita, Sayuri Nakamura, Kanemitsu Ootsu, Takanobu Baba:
Recover-X: An Adaptive Router with Limited Escape Channels. ICPADS 2000: 272-279 - 1998
- [c1]Tsutomu Yoshinaga, Masaya Hayashi, Maki Horita, Y. Yamaguchi, Kanemitsu Ootsu, Takanobu Baba:
A Cost and Performance Comparison for Wormhole Routers based on HDL Designs. ICPADS 1998: 375-382
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