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ORCIDHechen Wang
- > Home > Persons > Hechen Wang
Publications
- 2020
[j3]Hechen Wang
, Fa Foster Dai, Zhan Su, Yanjie Wang:
Sub-Sampling Direct RF-to-Digital Converter With 1024-APSK Modulation for High Throughput Polar Receiver. IEEE J. Solid State Circuits 55(4): 1064-1076 (2020)- 2019
- [c8]Zhan Su, Hechen Wang, Haoyi Zhao, Zhenqi Chen, Yanjie Wang, Fa Foster Dai:
A 280MS/s 12b SAR-Assisted Hybrid ADC with Time Domain Sub-Range Quantizer in 45nm CMOS. CICC 2019: 1-4 - [c7]Zhan Su, Hechen Wang, Haoyi Zhao, Xiao Liu, Fa Foster Dai:
An 8-bit 80-MS/s Fully Self-Timed SAR ADC with 3/2 Interleaved Comparators and High-Order PVT Stabilized HBT Bandgap Reference. ISCAS 2019: 1-4 - [c5]Hechen Wang, Zhan Su, Haoyi Zhao, Yanjie Wang, Fa Foster Dai:
A 3.8 mW Sub-Sampling Direct RF-to-Digital Converter for Polar Receiver Achieving 1.94 Gb/s Data Rate with 1024-APSK Modulation. VLSI Circuits 2019: 82- - 2018
- [j2]Hechen Wang, Fa Foster Dai, Hua Wang:
A Reconfigurable Vernier Time-to-Digital Converter With 2-D Spiral Comparator Array and Second-Order ΔΣ Linearization. IEEE J. Solid State Circuits 53(3): 738-749 (2018) - [c4]Taiyun Chi, Hechen Wang, Min-Yu Huang, Fa Foster Dai, Hua Wang:
A bidirectional lens-free digital-bits-in/-out 0.57mm2 terahertz nano-radio in CMOS with 49.3mW Peak power consumption supporting 50cm Internet-of-Things communication. CICC 2018: 1-4 - 2017
- [j1]Dongyi Liao, Hechen Wang, Fa Foster Dai, Yang Xu, Roc Berenguer, Sara Munoz Hermoso:
An 802.11a/b/g/n Digital Fractional-N PLL With Automatic TDC Linearity Calibration for Spur Cancellation. IEEE J. Solid State Circuits 52(5): 1210-1220 (2017) - [c3]Taiyun Chi, Hechen Wang, Min-Yu Huang, Fa Foster Dai, Hua Wang:
A bidirectional lens-free digital-bits-in/-out 0.57mm2 Terahertz nano-radio in CMOS with 49.3mW peak power consumption supporting 50cm Internet-of-Things communication. CICC 2017: 1-4 - [c2]Hechen Wang, Fa Foster Dai, Hua Wang:
A 330μW 1.25ps 400fs-INL vernier time-to-digital converter with 2D reconfigurable spiral arbiter array and 2nd-order ΔΣ linearization. CICC 2017: 1-4 - [c1]Hechen Wang, Fa Foster Dai:
A 14-Bit, 1-ps resolution, two-step ring and 2D Vernier TDC in 130nm CMOS technology. ESSCIRC 2017: 143-146
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