Haile Yu

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Philip H. W. Leong

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Publications

2012
[j1]
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Haile Yu, Philip Heng Wai Leong, Qiang Xu:
An FPGA Chip Identification Generator Using Configurable Ring Oscillators. IEEE Trans. Very Large Scale Integr. Syst. 20(12): 2198-2207 (2012)
2011
[c9]
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  - conf/fpga/YuXL11
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Haile Yu, Qiang Xu, Philip Heng Wai Leong:
On timing yield improvement for FPGA designs using architectural symmetry (abstract only). FPGA 2011: 278
[c8]
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Haile Yu, Qiang Xu, Philip Heng Wai Leong:
On Timing Yield Improvement for FPGA Designs Using Architectural Symmetry. FPL 2011: 539-544
2010
[c7]
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Haile Yu, Qiang Xu, Philip Heng Wai Leong:
Fine-grained characterization of process variation in FPGAs. FPT 2010: 138-145
[c6]
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Haile Yu, Philip Heng Wai Leong, Qiang Xu:
An FPGA chip identification generator using configurable ring oscillator. FPT 2010: 312-315
2009
[c5]
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  - conf/fpl/YuLHMGZ09
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Haile Yu, Philip Heng Wai Leong, Heiko Hinkelmann, Leandro Möller, Manfred Glesner, Peter Zipf:
Towards a unique FPGA-based identification circuit using process variations. FPL 2009: 397-402
[c4]
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  - conf/fpt/HungWYCL09
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Eddie Hung, Steven J. E. Wilton, Haile Yu, Thomas C. P. Chau, Philip Heng Wai Leong:
A detailed delay path model for FPGAs. FPT 2009: 96-103
2008
[c3]
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  - conf/fpga/YuCL08
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Haile Yu, Yuk Hei Chan, Philip Heng Wai Leong:
FPGA interconnect design using logical effort. FPGA 2008: 257
[c2]
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Haile Yu, Yuk Hei Chan, Philip Heng Wai Leong:
FPGA interconnect design using logical effort. FPL 2008: 447-450

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