Roland E. Wunderlich

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with James C. Hoe

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Publications

2006
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Thomas F. Wenisch, Roland E. Wunderlich, Michael Ferdman, Anastassia Ailamaki, Babak Falsafi, James C. Hoe:
SimFlex: Statistical Sampling of Computer System Simulation. IEEE Micro 26(4): 18-31 (2006)
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Roland E. Wunderlich, Thomas F. Wenisch, Babak Falsafi, James C. Hoe:
Statistical sampling of microarchitecture simulation. ACM Trans. Model. Comput. Simul. 16(3): 197-224 (2006)
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Thomas F. Wenisch, Roland E. Wunderlich, Babak Falsafi, James C. Hoe:
Statistical sampling of microarchitecture simulation. IPDPS 2006
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Thomas F. Wenisch, Roland E. Wunderlich, Babak Falsafi, James C. Hoe:
Simulation sampling with live-points. ISPASS 2006: 2-12
2005
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  - conf/sigmetrics/WenischWFH05
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Thomas F. Wenisch, Roland E. Wunderlich, Babak Falsafi, James C. Hoe:
TurboSMARTS: accurate microarchitecture simulation sampling in minutes. SIGMETRICS 2005: 408-409
2004
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Nikolaos Hardavellas, Stephen Somogyi, Thomas F. Wenisch, Roland E. Wunderlich, Shelley Chen, Jangwoo Kim, Babak Falsafi, James C. Hoe, Andreas Nowatzyk:
SimFlex: a fast, accurate, flexible full-system simulation framework for performance evaluation of server architecture. SIGMETRICS Perform. Evaluation Rev. 31(4): 31-34 (2004)
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Roland E. Wunderlich, James C. Hoe:
In-system FPGA prototyping of an itanium microarchitecture. FPGA 2004: 255
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Roland E. Wunderlich, James C. Hoe:
In-System FPGA Prototyping of an Itanium Microarchitecture. ICCD 2004: 288-294
2003
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Roland E. Wunderlich, Thomas F. Wenisch, Babak Falsafi, James C. Hoe:
SMARTS: Accelerating Microarchitecture Simulation via Rigorous Statistical Sampling. ISCA 2003: 84-95

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